Provided by: edaa
Date Added: Mar 2009
As industry moves towards many-core chips, Networks-on-Chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early stage estimation of NoC power has become crucially important. ORION was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes - the Intel 80-core Teraflops chip and the Intel Scalable Communications Core (SCC) chip - the authors saw significant deviation that can lead to erroneous NoC design choices.