Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware

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Provided by: edaa
Topic: Hardware
Format: PDF
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, the authors propose a logic design style, called as Precharge Masked Reed-Muller Logic (PMRML) to overcome the glitch and Dissipation Timing Skew (DTS) problems in design of DPA-resistant cryptographic hardware. Both problems can significantly reduce the DPA-resistance. To their knowledge, the DTS problem and its countermeasure have not been reported. The PMRML design can be fully realized using common CMOS standard cell libraries. Furthermore, it can be used to implement universal functions since any Boolean function can be represented as the Reed-Muller form.
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