Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations

Provided by: edaa
Topic: Hardware
Format: PDF
The simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). The SystemC TLM2.0 (Transaction Level Modeling) approach accelerates the simulation by using Interface Method Calls (IMC) to implement the communications between hardware components. Another source of speedup can be exploited by parallel simulation. Multi-core workstations are becoming the mainstream, and SMP workstations will soon contain several tens of cores. The standard SystemC simulation engine uses a centralized scheduler that is clearly the bottleneck for a parallel simulation.

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