Parallel Structurally-Symmetric Sparse Matrix-Vector Products on Multi-Core Processors

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Provided by: Universidade Federal do Paraná
Topic: Hardware
Format: PDF
The authors consider the problem of developing an efficient multi-threaded implementation of the matrix-vector multiplication algorithm for sparse matrices with structural symmetry. Matrices are stored using the Compressed Sparse Row-Column format (CSRC), designed for pro ting from the symmetric non-zero pattern observed in global finite element matrices. Unlike classical compressed storage formats, performing the sparse matrix-vector product using the CSRC requires thread-safe access to the destination vector. To avoid race conditions, they have implemented two partitioning strategies.
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