Parallel Transistor Level Full-Chip Circuit Simulation

Provided by: edaa
Topic: Hardware
Format: PDF
In this paper, the authors present a fully parallel transistor level full-chip circuit simulation tool with SPICE-accuracy for general circuit designs. The proposed overlapping domain decomposition approach partitions the circuit into a linear sub-domain and multiple non-linear sub-domains based on circuit non-linearity and connectivity. Parallel iterative matrix solver is used to solve the linear domain while non-linear sub-domains are parallelly distributed into different processors topologically and solved by direct solver. To achieve maximum parallelism, device model evaluation is done parallelly.

Find By Topic