Parameter Optimization Performance Analysis of 4-Bit CMOS Layout for Adder

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Provided by: International Journal of Engineering Innovations and Research (IJEIR)
Topic: Hardware
Format: PDF
A full adder is a combinational circuit that performs the arithmetic sum of three bits: A, B and a carry in, C, from a previous addition. Also, as in the case of the half adder, the full adder produces the corresponding Sum (S) and a Carry out (Co). In this paper, the authors design 4-bit CMOS layout for 4- bit full adder with the help of half adder and other logic gates. In this paper, they calculate power dissipation of gates and modules which they used in designing and also calculate the no. of transistors which were used in designing of gates. The result of simulation of adder layout is in Microwind2.
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