Institute of Electrical & Electronic Engineers
Upcoming processor architectures support parallel processing on different levels. Multiple Processing Elements (PEs) run in parallel. The PEs consists of several functional units and the functional units allow Sub-Word Parallelism (SWP), i.e. the parallel execution of operations with low data word width. In this paper, a parameterized mapping of algorithms onto massively parallel Processor Architectures (PAs) is derived which exploits both parallelism on PA and SWP on PE level. It establishes a correlation between the parameters of the algorithms and the parameters of the PA, which enables optimization strategies with respect to several expense factors of the PA.