Partitioning Three Dimensional IC in Circuit Level

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Provided by: Applications of Engineering Technology and Science (AETS)
Topic: Hardware
Format: PDF
More number of silicon die has been vertically stacked and allowed for three dimensional integration. Using silicon vias the stacked die are strongly integrated. Short vertical connections used in die are replaced with long global wires. Previous paper has been represented only general test architecture for pre bond testability. This paper proposes new methods for partitioning only at circuit level. The individual circuits having gates and circuits could be split across die layers. The authors are using port split register unit and adder unit. For every circuit three dimensional view, planar and layouts are produced. Their paper verifies power measurements, performance, monitor and the coverage of testing.
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