Provided by: Iosrjournals
In this paper, performance analysis comparison of a conventional Wallace multiplier and a reduced complexity Wallace multiplier is presented. Performance comparison is done in terms of power, delay, power delay product and complexity in terms of number of MOS transistors. The multipliers are designed by using cadence virtuoso in 180nm CMOS technology and their performance characteristics are analyzed. Performance improvement of the designed 4x4 bit reduced complexity Wallace multiplier with respect to the designed 4x4 bit conventional Wallace multiplier in terms of number of transistors, delay and power delay product are found to be 12.05%, 9.42% and 4.98% respectively.