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In this paper, design of two different array multipliers are presented, one by using Carry-Look-Ahead (CLA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper, were all modeled using VHDL (Very High speed integration hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performance parameters i.e. area, speed and power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field.