Performance Analysis of Fine Grain Pipelined Fixed Width Multiplier Architecture for FIR Filter Application

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Provided by: Society of Engineering Science and Technology
Topic: Hardware
Format: PDF
The authors propose this paper based on architectural manipulation of Fixed Width Multiplier (FWM), designed for FIR filter to lower down the dynamic power consumption. The speed and power consumption of DSP algorithms like FIR filter which uses multiplier as a core computationally complex design is governed by the critical path of the multiplier used. To lower down the power consumption or increase the speed, the cut set theory of taking a feed forward cut set is used in this paper.
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