Performance Analysis of Floating Point Adder Using VHDL on Reconfigurable Hardware
Floating point addition is more difficult than multiplication because alignment of mantissa is required before mantissa addition. The main objective of implementation of floating point adder on reconfigurable hardware i.e. on Virtex is to utilize less chip area with less combinational delay and faster speed. Less combinational delay means less latency i.e. less time is required to appear an output after the input response is applied and if there is less latency then there will be the faster speed and lesser the clock period.