Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices

In this paper, the authors explain the performance analysis of gate-all-around silicon nano-wire with 80nm diameter field effect transistor based CMOS based device utilizing the 45nm technology. Simulation and analysis of Nano-Wire (NW) CMOS inverter show that there is the reduction of 70% in leakage power and delay minimization of 25% as compared with 180nm channel length. Gate-All-Around (GAA) configuration provides better and low Drain Induced Barrier Lowering (DIBL) 63.3mV/V and competent sub-threshold slope 95mV/V.