Performance Analysis of Novel Domino XNOR Gate in Sub 45nm CMOS Technology

Provided by: WSEAS
Topic: Hardware
Format: PDF
In this paper, the authors propose three new versions of domino XNOR gate circuits. The proposed circuits adopt mixed N and P type transistor in the pull-down network. All performance parameters are measured at 25 deg. C and 110 deg. C. In first proposed circuit, it lowers the total leakage power by 8% to 12%, PDP is reduced by 6% to 9% and A.C noise margin is enhanced by 7% as compared to standard n-type XNOR gate. Second proposed circuit having multiple threshold voltage, lowers the total leakage power by 47% to 57%, PDP is reduced by 80% to 86% and A.C noise margin is enhanced by 33% as compared to standard n-type XNOR gate.

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