International Journal of Emerging Technology and Advanced Engineering (IJETAE)
The CO-ordinate Rotation DIgital Computer (CORDIC) was developed by the researcher to compute the rotation of two dimensional vector. Although full radix 4 cordic algorithm is efficient compared to standard radix 2 cordic processor. Scale factor over head causes its improvement to be limited. In this paper, radix 4 cordic algorithm which incorporates parallelism and pipelining is proposed. A 16 bit radix- 4 cordic architecture is implemented of the available FPGA board. The latency of the architecture is eight clock cycles. It operates at 57.484 MHz of clock rate with power consumption of 265mW.