Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

Provided by: UC Regents
Topic: Hardware
Format: PDF
The performance and threshold voltage variability of Fully Depleted Silicon-On-Insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively.

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