Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Dynamically Reconfigurable Processor (DRP) developed by NEC electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time multiplexed execution, the authors have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, they analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

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