Performance Balancing: Software-Based On-Chip Memory Management for Effective CMP Executions

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Provided by: Kyushu University
Topic: Hardware
Format: PDF
In this paper, the authors propose the concept of performance balancing, and report its performance impact on a Chip Multi-Processor (CMP). Integrating multiple processor cores into a single chip, or CMPs, can achieve higher peak performance by means of exploiting thread level parallelism. However, the off-chip memory bandwidth which does not scale with the number of cores tends to limit the potential of CMPs. To solve this issue, the technique proposed in this paper attempts to make a good balance between computation and memorization.
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