Performance Comparison of RS Decoder on Family of MAX CPLD Using Verilog HDL

Provided by: Creative Commons
Topic: Hardware
Format: PDF
Forward Error Correction (FEC) in transceiver (transmitter/receiver pair) is used to deliver information from a source (transmitter) to a destination (receiver) through a noisy communication channel with a minimum of errors. In this paper, design of Reed-Solomon (RS) decoder and perform this decoder on family of MAX CPLD and compare the performance based on area occupied by the design and the speed at which the design can run and power dissipation. The author applied forward error correction system to improve the overall performance of the system. The implementation is written in Verilog HDL based on Barlekamp Massy, Forney and Chien search algorithm.

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