Performance Effects of a Cache Miss Handling Architecture in a Multi-core Processor

Provided by: Norwegian University of Science and Technology
Topic: Hardware
Format: PDF
Multi-core processors, also called Chip Multi-Processors (CMPs), have recently been proposed to counter several of the problems associated with modern superscalar microprocessors: limited Instruction Level Parallelism (ILP), high power consumption and large design complexity. However, the performance gap between a processor core and main memory is large and growing. Consequently, multi-core architectures must invest in techniques to hide the large memory latency. One way of doing this is to use non-blocking or lockup-free caches. The key idea is that a cache can continue to service requests while one or more misses are being processed at a lower memory hierarchy level.

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