Performance Enhancement of Double Gate Junctionless Transistor Using High-K Spacer

Provided by: Institute of Research and Journals (IRAJ)
Topic: Hardware
Format: PDF
Junction-Less Transistors (JLTs) were proposed as a promising metal-oxide-semiconductor FET architecture for scaling. Earlier, transistor have junction between source and substrate and drain and substrate. Beyond 90nm it is too much difficult to fabricate a transistor because it needs a sharp doping concentration gradient with a few couple of nano-meters. But junction-less transistor have same doing across source channel and drain, so it is too much easier to fabricate and cheaper. JLTs have many advantages over standard MOSFETs such as better short channel effects performance (reduced Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (SS) degradation) resulting better scalability, less variation in drain current with doping concentration, greatly simplified fabrication process and low thermal budgets.

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