Performance Enhancement w.r.t. Time in Hetrogeneous Network on Chip Architecture
With the increase in integration density and complexity of SOC (System On Chip), the conventional interconnects are not suitable to fulfill the demands. The application of traditional network technologies in the form of network-on-chip is a possible solution. NoC design space has numerous variables. As an improved topology is selected complexities decrease and power-efficiency increases. In this paper, the main research field in network-on-chip design focusing on optimized topology design is analyzed. The simulation is modeled using a conventional network simulator tool ns-2, in which by selecting proposed topology 35.7% reduction in traversing the longest path is observed.