Performance Estimation Technique for an On-Chip Bus Employing Fixed Priority Arbitration Policy

Provided by: AICIT
Topic: Hardware
Format: PDF
In this paper, the authors present the bus model for predicting an on-chip bus throughput at the beginning of the SoC design cycle. In particular, they focus on analyzing the effect of the employed bus arbitration policy on the performance of a target SoC design, in particular, a multimedia SoC (System-on-Chip) one. They evaluate the bus model by applying probabilistic methodology to the well-defined target multimedia SoC. The simulation results show that the proposed bus model achieves almost 80% accuracy compared commercial low-level simulator even though it is based on system-level model.

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