Performance Evaluation of a 16.16 Fixed-Point Multiplier Implemented on the FALCON-A Processor

Provided by: The Second International Conference on Communications and Information Technology
Topic: Data Centers
Format: PDF
This paper describes the implementation of a fixed point multiplier (using the 16.16 format) on the FALCON-A processor. Special assembly language coding techniques have been used to achieve the optimum code size along with minimum truncation error and minimum execution time. It is expected that this information will provide an additional insight into various trade-offs in processor design and memory usage to students taking courses in this area. Students will also be able to learn advanced assembly language programming techniques. Evaluation of various performance parameters related to the FALCON-A architecture have been included at the end.

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