Performance Evaluation of CDMA Router for Network - on - Chip
Traditionally, ICs have been designed with dedicated point-to-point connections, with one wire dedicated to each signal. This paper presents the performance evaluation of router based on Code Division Multiple Access (CDMA) technique for Network-on-Chip (NoC). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using ModelSim XE III 6.2C. The delay and throughput values are obtained for variable payload sizes. Throughput power and delay power characteristics are also verified for NoC.