Performance Evaluation of Interconnection Schemes for Shared Cache Memory Multi-core Architectures

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Provided by: WSEAS
Topic: Hardware
Format: PDF
Current Systems-on-Chips (SoCs) designs integrate an increasingly large number of designed cores and their number is predicted to increase significantly in the near future. This paper focuses on the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory. It shows that having shared cache memory contributes to the performance improvement; however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores.
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