Performance Evaluation of Packet Classification on FPGA-Based TCAM Emulation Architectures

Provided by: Institute of Electrical & Electronic Engineers
Topic: Mobility
Format: PDF
Packet classification techniques are continuously challenged as network bandwidth increases and new services are deployed. Ternary Content Addressable Memories (TCAMs) have traditionally been used for scenarios requiring high-speed packet processing. However, TCAM-based classification suffers from high power consumption and clock rate limitations. Among several proposed solutions, TCAM emulation through RAM has emerged as a more flexible and energy-efficient strategy. On the other hand, Field-Programmable Gate Array (FPGA) devices have been evolving providing not only abundant logical resources but also an increasing number of integrated RAM blocks.

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