Performance Investigation of Reduced Complexity Bit-Flipping Using Variable Thresholds and Noise Perturbation

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Provided by: Institute of Electrical and Electronics Engineers
Topic: Hardware
Format: PDF
The near Shannon capacity approaching Low-Density Parity-Check (LDPC) linear block codes are now in widespread use in modern systems including the Long Term Evolution Advanced (LTE-A) cellular, 802.11n Wi-Fi and DVB-S2 satellite communications standards. The decoders based on the iterative belief propagation algorithm provide near optimum performance but also have very high computational complexity. Therefore, significant research has recently focused on reduced complexity architectures based on the group of so-called bit-flipping algorithms. In the basic bit-flipping algorithm the number of failed parity checks for each bit is computed and the bit with the maximum failed parity checks is inverted.
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