Physical Design Implementation of Processor Torpedo at Different OCV Scenarios -40, 25, 125 Degree Celsius of an ASIC Design Chip

In this paper the authors basically studies the physical design implementation of torpedo processor which incorporates 32 macros in overall and 43000 cell instances. They had 5 clocks, 3 propagated and 2 generated clock in a die size of 5.9 mm square which operated at a frequency of 400 megahertz having a supply voltage of 1.8 volts .The technology which they worked was 180 nm technology and working on the IC compiler tool from synopsys and then moving on to static timing analysis part on the prime time tool from synopsys and then further moving on to drc/lvs checking on the tool Calibre from mentor graphics.

Provided by: International Journal of Engineering and Advanced Technology (IJEAT) Topic: Hardware Date Added: Feb 2014 Format: PDF

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