Physical Scaling Limits of FinFET Structure: A Simulation Study

Provided by: Academy & Industry Research Collaboration Center
Topic: Hardware
Format: PDF
As technologies are scaled down in deep sub-half micron regime, the conventional bulk MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) faces several challenges like higher DIBL, poor sub-threshold swing collectively known as SCEs. Moreover, the gate oxide thickness has been reached to its physical limit with the scaling i.e. below 1nm and increasing gate leakage current is one of the most challenging tasks for future scaling. It seems impossible to further scale down the gate oxide beyond the inter-atomic distance.

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