Physical Vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs

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Provided by: Massachusetts Institute of Technology
Topic: Hardware
Format: PDF
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an important design choice that affects how these networks scale. Most current on-chip networks use 2-D mesh topologies which do not scale due to their large diameter and energy inefficiency. To tackle the scalability problem of 2-D meshes, various physical express topologies and virtual express topologies have been proposed. In addition, recently proposed link designs like capacitive driven low-swing interconnects can help lower link power and latency, and can favor these bypass designs.
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