Pipeline Exploration for Reconfigurable Targets

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Provided by: Imperial College London
Topic: Data Centers
Format: PDF
The ability to compile software into an efficient, synthesisable hardware description can dramatically reduce the design times for embedded systems that require the acceleration offered by hardware coprocessors. Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. Methods have been developed for soft-ware compilers that extend loop pipelining to levels above the innermost loop but they have yet to be extended for hardware.
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