Pipelined CORDIC Architecture for FFT Processor Implementation on FPGA

Provided by: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)
Topic: Hardware
Format: PDF
In this paper, the authors study of an efficient CORDIC algorithm for FFT processor implementation on FPGA. Due to use of radix-4 speed get increases than radix-2 in FFT computation. For twiddle factor calculation CO-ordinate Rotation DIgital Computer (CORDIC) algorithm is used, which help to reduce the computation time and make processor faster. The CORDIC provides the opportunity to calculate all the required functions in a rather simple and elegant fashion. This paper, actual Implementation of FFT processor on FPGA will be done using VHDL.

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