Pipelined Floating-Point Arithmetic Unit (FPU) for Advanced Computing Systems using FPGA

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Provided by: International Journal of Engineering and Advanced Technology (IJEAT)
Topic: Hardware
Format: PDF
Field Programmable Gate Arrays (FPGA) is increasingly being used to design high-end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. An efficient design of floating-point adder onto an FPGA offers major area and performance overheads.
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