Pipelined Implementation of Dynamic Rijndael S-Box
Pipelined architecture for S-Box is proposed in this paper. ROM based look-up table implementation of S-Box requires more memory and introduces unbreakable delay for its access. Pipelined S-Box of combinational logic based implementation gives higher throughput and less delay as compared to that of no pipelined S-Box. 5, 6 and 7 stages of pipelined architecture have been simulated using Xilinx 9.2i for SPARTAN-3 FPGA. The result from place and route reports shows increase in maximum clock frequency at the cost of increased number of used slices.