Pipelined Parallel FFT Architecture
In this paper, an optimized efficient VLSI architecture of a pipeline Fast Fourier Transform (FFT) processor capable of producing the reverse output order sequence is presented. This paper presents Radix-2 multipath delay architecture for FFT calculation. The implementation of FFT in hardware is very critical because for calculation of FFT number of butterfly operations i.e. number of multipliers requires due to which hardware gets increased means indirectly cost of hardware is automatically gets increased. Also multiplier operations are slow, that's why it limits the speed of operation of architecture.