Institute of Electrical & Electronic Engineers
In this paper, the authors present a Chip-level post-complementary Metal Oxide Semiconductor (CMOS) processing technique for 3-D integration and Through-Silicon-Via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple alternative to spin-coated resist. Unlike conventional photolithography methods, the technique allows resist patterning on very high topography, and therefore chip-level photolithography can be done without using any wafer reconstitution approach. Moreover, this paper proposes a via sidewall passivation method which eliminates dielectric etching at the bottom of the via and simplifies the whole integration process.