International Journal of Industrial Electronics and Electrical Engineering (IJIEEE)
In this paper, the authors provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, this paper focuses on the reduction of the power dissipation, which is showing an ever-increasing growth with the scaling down of the technologies. Then, to limit the power dissipation, alternative solutions at each level of abstraction are proposed. The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers.