Power-Aware Mapping for Network-on-Chip Architectures Under Bandwidth and Latency Constraints

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Provided by: Zhejiang Sci-Tech University
Topic: Hardware
Format: PDF
In this paper, the authors investigate the bandwidth- and latency-constrained IP mapping problem that maps a given set of IP cores onto the tiles of a mesh-based Network-on-Chip (NoC) architecture to minimize the power consumption due to intercore communications. By examining various applications' communication characteristics shown in their communication trace graphs; two distinguishable connectivity templates are realized: the graphs with tightly coupled vertices and those with distributed vertices. Different mapping heuristics are developed for these templates: tightly coupled vertices are mapped onto tiles that are close to each other while the distributed vertices are mapped following a graph partition scheme.
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