Power-Aware Performance Increase Via Core/Uncore Reinforcement Control for Chip-Multiprocessor

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Network-on-Chips (NoCs) have emerged as the backbone for the inter-core communication of a Chip Multi-Processor (CMP). This paper evaluates and analyzes the advantages of managing the processing cores and the on-chip communication fabric in synergy for the purpose of performance increase under power constraints. A semi-supervised Reinforcement Learning (RL) based approach is proposed for performing Dynamic Voltage and Frequency Scaling (DVFS) so as to enable the efficient usage of the available on-chip power budget while maximizing performance.
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