Power-Constrained Test Scheduling for Multi-Clock Domain SoCs

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Provided by: edaa
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In this paper, the authors present a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. They also propose a test scheduling algorithm for multi-clock domain SoCs to minimize test time under power constraint. In the proposed method, they use virtual TAM to solve the frequency gaps between cores and the ATE, and also to reduce power consumption of a core during test while maintaining the test time of the core. Experimental results show the effectiveness of their method not only for multi-clock domain SoCs, but also for single-clock domain SoCs with power constraints.
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