Institute of Electrical & Electronic Engineers
In this paper, the authors have presented novel microarchitectural techniques for reducing the power overheads of RMT. When executing leading and trailing redundant threads, they take advantage of the fact that the leading thread prefetches data and resolves branches for the trailing thread. The results of the leading thread also allow the trailing core to implement a perfect register value predictor. All of the information from the leading thread makes it possible for the trailing thread to achieve high IPC rates even with an in-order core, thereby justifying the cost of high intercore traffic.