Power Efficient Design of Multiplexer Using Adiabatic Logic
In this paper, the authors provide low power solutions for Very Large Scale Integration (VLSI) design. The dynamic power consumption of CMOS circuits is rapidly becoming a major concern in VLSI design. By adiabatic technique dynamic power consumption in pull up network can be reduced and energy stored on the load capacitance can be recycled. In this paper, different logic style multiplexes have been analyzed and low power 2:1 multiplexer is designed using positive feedback adiabatic logic. It has been observed that adiabatic multiplexer consumes 53.1% less power than Energy Economized Pass-transistor Logic (EEPL) multiplexer.