Power Efficient Redundant Execution for Chip Multiprocessors

In this paper, the authors describe the design of a power efficient micro-architecture for transient fault detection in Chip Multi-Processors (CMPs). They introduce a new per-core Dynamic Voltage and Frequency Scaling (DVFS) algorithm for their architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, they estimate that their architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.

Provided by: Linkoping University Topic: Hardware Date Added: May 2009 Format: PDF

Find By Topic