Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity

Provided by: The University of Tulsa
Topic: Hardware
Format: PDF
The ever increasing demand for high clock speeds and the desire to exploit abundant transistor budgets have resulted in alarming increases in processor power dissipation. Partitioned architectures have been proposed in recent years to address scalability concerns in future billion-transistor microprocessors. The authors' analysis shows that increasing processor resources in a clustered architecture results in a linear increase in power consumption, while providing diminishing improvements in single-thread performance. To preserve high performance to power ratios, they claim that the power consumption of additional resources should be in proportion to the performance improvements they yield.

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