Power Efficient Voltage Islanding for Systems-on-Chip from a Floorplanning Perspective

Provided by: edaa
Topic: Hardware
Format: PDF
Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this voltage islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address several of these issues.

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