Power Optimization by Using Multi-Bit Flip-Flops

Provided by: International journal of Engineering and Management Research (IJEMR)
Topic: Hardware
Format: PDF
A significant portion of the total power consumption in high performance digital circuits in deep submicron region is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. Clock gating is a predominant technique used for power saving. It is observed that the commonly used synthesis based gating still leaves a large amount of redundant clock pulses. Data-driven gating aims to disable these. To reduce the hardware overhead involved, Flip-Flops (FFs) are grouped so that they share a common clock enabling signal.

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