Power Optimization in 3 Bit Pipelined ADC Structure
The pipelined Analog-to-Digital Converter (ADC) is an attractive architecture for high-speed data conversion in CMOS technologies. However, its linearity is limited due to its reliance on precise analog component matching and signal processing. This paper presents the systematic design approach of a low-power, medium resolution, high-speed pipelined Analog-to-Digital Converter (ADC). Two different design approach of 3 bit structure, frequency of 5 GHZ, supply voltage 1.2 V with slight modification implemented in microwind software. By simulation their power dissipation calculated, measured 50% less power consumed in modified pipelined ADC design.