Power Optimization in Digital Circuits Using Modified Ultra Low Power NAND Gates

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
The design of CMOS VLSI circuits is becoming more complex as the leakage power consumption is posing a serious issue now-a-days. Technological modification, reduction of threshold voltage and device geometry contributes to leakage power. The demands for electronic devices that are battery powered are increasing day-by-day. So, the portable devices like notebooks, hearing aids and personal communication devices need to be realized with low power consumption. In the proposed approach, three digital circuits have been designed.
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