Power Optimization of GCD Processor Using Low Power Spartan 6 FPGA Family

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Provided by: World Academic Industry Research Collaboration Organization (WAIRCO)
Topic: Hardware
Format: PDF
In this paper, the authors have done an extension of work using Spartan-3 FPGA family. Power dissipation is an important factor to be taken into consideration. Simulations are done using Spartan-6 and because of its good features and it's capability of having 42% less power consumption and 12% increased performance over previous generation devices. Arithmetic and Logic Unit (ALU) is being implemented which has a capability of doing arithmetic and logical operation along with calculation of Greatest Common Divisor (GCD) using Euclid's and Stein's algorithm.
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